Cadence has revealed its LPDDR5X 9600Mbps memory IP system solution, designed for enterprise and data centre apps seeking high reliability. The solution synergises Cadence’s LPDDR5X IP with Microsoft’s RAIDDR ECC coding schema, aiming to offer a blend of high performance, reduced power use, and reliability.
LPDDR5X supports energy-efficient, high-performance operation in data centres for AI, HPC, and other demanding workloads. Previously, hyperscalers had to balance power, performance, and area (PPA) with the reliability, availability, and serviceability (RAS) provided by DDR5 memory technology.
Built upon LPDDR5X DRAM technology, the solution presents RAS capabilities, maintaining an optimal PPA balance in a neat form factor.
Supporting speeds up to 9600Mbps, it provides sideband ECC performance comparable to traditional DDR5 ECC implementations, suitable for data centre environments.
Central to the system is Microsoft’s RAIDDR ECC coding schema. Designed for near single-device data correction (SDDC), the algorithm offers precise fault detection with minimal logic overhead.
RAIDDR aims to match the protective qualities of symbol-based ECC, commonly associated with DDR5 RDIMM applications.
The solution aims to provide clients with the following capabilities:
- 40-bit channel support leveraging LPDDR5X DRAM
- 9600Mbps performance with minimal power drain
- Enterprise-grade RAS with DDR5-type symbol-based ECC assurance
- Sideband ECC to optimise channel bandwidth
- Compact design for space-efficient systems
This memory solution extends Cadence’s offerings for enterprise and data centres. Its LPDDR6 system, launched in July 2025 at 14.4Gbps, supports higher-speed memory applications in enterprise and data centres.
Cadence's memory IP frameworks aims to suit high-performance AI training and inferencing paradigms. The company also offers a portfolio of silicon-verified, PPA-refined memory and interface IP for HPC and AI tasks.
