Synopsys targets hyperscale data centres

New DesignWare 56G Ethernet PHY supporting PAM-4 and NRZ signaling targets 100G, 200G, and 400G Ethernet applications.

  • 5 years ago Posted in
Synopsys has introduced the DesignWare® 56G Ethernet PHY IP for emerging 400 gigabit-per-second (Gbps) hyperscale data center system-on-chips (SoCs). The advanced 56G Ethernet PHY architecture incorporates Synopsys' silicon-proven data converters with a configurable transmitter and digital signal processor (DSP)-based receiver to deliver the best power and performance tradeoffs for the target application. To meet the bandwidth needs of leaf-spine architectures, the PHY supports single and aggregated link rates from 10G to 400G Ethernet, while meeting the PAM-4 and NRZ signaling. In addition, the PHY exceeds the performance requirements of OIF and IEEE standards for chip-to-chip, backplane, and copper/optical cable interfaces. The combination of Synopsys' 56G Ethernet PHY, digital controllers, verification IP, and source code test suites gives designers a complete Ethernet IP solution for their networking data center systems.

For a more robust timing recovery and better jitter performance, the 56G Ethernet PHY receiver features a multi-loop clock and data recovery circuit, as well as a full-featured DSP. The unique architecture of the PAM-4 transmitter allows for precise feed forward equalization to achieve channel performance requirements. The 56G Ethernet PHY's scalable architecture provides a foundation for next-generation 800G Ethernet applications requiring 112G connectivity.

"The growing amount of bandwidth required in the data center is increasing the workload demand on the network infrastructure," said John Koeter, vice president of marketing for IP at Synopsys. "Synopsys' DesignWare 56G Ethernet IP allows designers to meet the high-performance Ethernet connectivity requirements of 400G hyperscale data center SoCs with less risk."

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